The Use of Multithreaded Processors in DASH

DASH is a scalable shared memory multiprocessor architecture which employs directory based cache coherence. Due to the physical distribution of the memory in DASH, there is potential for long memory latency. Although a number of latency reducing and hiding techniques such caching, a weaker memory consistency model, and pre-fetching are employed by DASH, the use of Multithreaded processors is not currently included in the design. In this paper, the use of Multithreaded processors in the DASH architecture is examined. A processor architecture which incorporates multithreading with superscalar capabilities is proposed, and a general discussion of issues regarding multithreading as well as the incorporation of the proposed multithreaded processor into the existing DASH architecture is presented.